1. Field of the Invention
This invention generally relates to current switches. More particularly, the invention provides a boot-strapped current switch that is particularly well suited for use as a current switching element in a current mirror circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a typical current mirror 10. The current mirror 10 is a common circuit in which current flowing in one portion of the circuit is mirrored in another portion of the circuit. The current mirror 10 comprises a current source 12, and two metal-oxide semiconductor field-effect transistor (MOSFETs) 14 and 16. The current source 12 supplies a reference current (Iref) to one of the MOSFETs 14 which is mirrored in the second MOSFET 16 because the gate-source voltages of both MOSFETs 14 and 16 are substantially similar.
In many applications the current mirror 10 shown in FIG. 1 is modified to create a switched current mirror. Switched current mirrors are used, for example, in charge pumps and digital to analog converters (DACs). Examples of switched current mirrors typically used in a charge pump circuit are described below with reference to FIGS. 3-7.
FIG. 2 is a simplified diagram of a typical charge pump circuit 20. As shown in FIG. 2, a charge pump is conceptually equivalent to two switched current sources 22 and 24, where one current source 22 is biased to power and the other current source 24 is biased to ground. When the charge pump 20 receives a signal (UP) at switch 23 to connect the power-side current source 22, a positive current is generated at the charge pump output 26. Similarly, when the charge pump 20 receives a signal (DN) at switch 25, turning on the ground-side current source 24, a negative current is generated at the output 26.
FIGS. 3-5 show known charge pump designs wherein the current direction of the charge pump output (Iout) is controlled by opening and closing switches (UP and DN) connected to either the drain, source or gate of one of the MOSFETs in each current mirror. FIG. 3 is a circuit diagram of a known charge pump circuit 30 implemented with switched-drain current mirrors 32 and 34. The switched-drain charge pump 30 includes the two current mirrors 32 and 34, two current sources 33 and 35 and two switches (UP and DN) 36 and 38. The switches 36 and 38 are coupled to the drain terminals of one of the MOSFETSs in each current mirror 32 and 34 such that when the UP switch 36 is closed the charge pump 30 generates a positive output current (Iout), and when the DN switch 38 is closed the charge pump 30 generates a negative output current (Iout).
FIG. 4 is a circuit diagram of a known charge pump circuit 40 implemented with switched-source current mirrors 42 and 44. The switched-source charge pump 40 includes the two current mirrors 42 and 44, two current sources 43 and 45, and two switches (UP and DN). This switched-source charge pump 40 operates similarly to the switched-drain charge pump 30 shown in FIG. 3, except the switches (UP and DN) 46 and 48 are coupled to the source terminals of the respective current mirror MOSFETs. In both the switched-source charge pump 40 and the switched-drain charge pump 30, the UP and DN switches 36, 38, 46 and 48 are connected in the current path of the charge pump output (Iout), resulting in glitch currents when the switches are opened or closed. These glitch currents are typically caused by clock-feedthrough of the UP and DN control signal. Clock-feedthrough results when a control voltage on the gate of a MOSFET switch couples through to the drain terminal and/or source terminal via parasitic capacitances. Moreover, control switches 36, 38, 46 and 48 that are placed in the output current path typically require low resistances, thus large devices are usually employed; resulting in higher parasitic capacitances and consequent clock-feedthrough.
FIG. 5 is a circuit diagram of a known charge pump circuit 50 implemented with switched-gate current mirrors 52 and 54. The switched-gate charge pump 50 includes two current mirrors 52 and 54, two current sources 53 and 55, and two switches (UP and DN) 56 and 58. The switches 56 and 58 are respectively coupled to the FET gate terminals of the current mirrors 52 and 54. Operationally, the charge pump 50 generates a positive output current (Iout) when the UP switch 56 is opened, and a negative output current (Iout) when the DN switch 58 is opened. This charge pump circuit 50 reduces current glitches by removing the control switches (UP and DN) 56 and 58 from the output current path, but typically exhibits a relatively slow switching speed.
FIGS. 6(a)-6(d) show some typical switching circuits that may be used to implement the UP and DN switches 36, 38, 46, 48, 56 and 58 shown in FIGS. 3-5. All of the UP and DN switches 36, 38, 46, 48, 56 and 58 may be implemented, for example, as a singal n-type FET as shown in FIG. 6(a), as a singal p-type FET as shown in FIG. 6(b), or as a combination of FETs as shown in FIGS. 6(c) and 6(d). In FIG. 6, and in subsequent drawing figures throughout this application, true and inverted versions of the same signal are designated using an overbar convention. For instance, in FIGS. 6(b), 6(c) and 6(d), {overscore (DN)} is an inverted version of the DN signal.
FIG. 7 is a circuit diagram of a known current steering charge pump circuit 70. The charge pump circuit 70 includes two p-channel MOSFET transistors (PMOS) 72 and 74, two n-channel MOSFET transistors (NMOS) 76 and 78 and two current sources 80 and 82. Operationally, the charge pump 70 generates either a positive or negative output current (Iout) by switching between the two current sources 80 and 82. When the UP signal is low, the positive current source 80 is switched to the charge pump output (Iout) by the PMOS transistor 74, and the PMOS transistor 72 is off. Then, when the UP signal is high, the {overscore (UP)} signal is low and the current from source 80 is switched to ground by the PMOS transistor 72. In this manner, the current (Ip) from current source 80 is xe2x80x9csteeredxe2x80x9d between the charge pump output (Iout) and ground. In this example, ground is the xe2x80x9cdummy load,xe2x80x9d however voltages other than ground are also commonly used. Similarly, when the DN signal is high, the negative current source 82 is switched to the charge pump output (Iout) by NMOS 78. A high DN signal, and consequent low {overscore (DN)} signal, steers the current (Ip) from source 82 through NMOS 76. One skilled in the art will appreciate that current steering improves the speed of the charge pump because the current mirror is always on, supplying current to either the output load or the dummy load. This always-on condition, however, is often undesirable in power sensitive applications such as wireless communication devices. In addition, the PMOS transistor 74 and the NMOS transistor 78 are in series with the charge pump output current, and may consequently add glitch currents to the output due to clock-feedthrough.
A boot-strapped current switch is provided that includes a biasing network, a control signal, a transistor, a control switch and a boot-strapping circuit. The biasing network generates a substantially constant voltage on a biasing network output. The transistor has a control terminal, a first current-carrying terminal, and a second current-carrying terminal, wherein the first current-carrying terminal generates the output current of the current mirror, and the second current-carrying terminal is coupled to a first potential. The control switch is coupled between the biasing network output and the control terminal of the transistor, and is also coupled to the control signal. The control switch couples the first biasing network output to the control terminal of the transistor when the control signal is in a first state. The boot-strapping circuit is coupled between the control terminal of the transistor and a second potential, and is also coupled to the control signal. The first boot-strapping circuit injects the second potential onto the control terminal of the transistor when the control signal transitions from a second state to the first state in order to decrease the turn-on time of the transistor.